Spatial light modulators (SLMs) consist of an array of electronically addressable pixel elements and related control circuitry. A typical application is for image display, where light from each pixel is magnified and projected to a display screen by an optical system. The type of modulation depends on how the modulator is combined with an optical system.
A frequently used type of SLM is the deformable mirror device (DMD, also known as digital micromirror device), in which each pixel element is a tiny micromechanical mirror, capable of separate movement in response to an electrical input. Incident light may be modulated in direction, phase, or amplitude for reflection from each pixel.
For many applications, the SLM is binary in the sense that each pixel element may have either of two states. The element may be off, which means that it delivers no light. Or, the element may be on, which means that it delivers light at a maximum intensity. To achieve a viewer perception of intermediate levels of light, various pulse width modulation techniques may be used. These techniques are described in pending U.S. patent Ser. No. 07/678,761, entitled "DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System", assigned to the same assignee as the present application.
In general, pulse width modulation produces an integrated brightness by switching each pixel on or off for a period that corresponds to a binary number, during each frame. Pulse width modulation uses various schemes for loading the SLM, such as "bit-frame" loading, in which one bit per pixel for an entire frame is loaded at one time. Each pixel element has a memory cell. The entire array of memory cells is loaded with one bit per cell, then all pixel elements are set to correspond to that bit-frame of data. During the display time of the current bit-frame, data for the next bit-frame is loaded. Thus, for example, for 8-bit pixel brightness quantization, the SLM is loaded eight times per frame, one pixel per frame at a time. In one such method, the most significant bit is displayed for 1/2 of a frame period, the second most significant bit for 1/4 frame period, etc., with the least significant bit (LSB) representing a display time of 1/2.sup.n frame period, for n-bit brightness quantization.
A problem with existing pixel loading techniques is that they require at least one memory cell per pixel element. As the number of pixels per frame increases, the memory requirements for the SLM device results in increased costs and reduced manufacturing yields. A need exists for an SLM that has reduced circuitry for controlling the pixel elements.
Loading schemes that use a memory cell for every pixel element also limit the minimum time in which a pixel element can be set, to the time required to load a bit-frame into the memory array. When pulse width modulation is used, the display time for the LSB is the shortest display time. During this LSB time, the data for the next frame must be loaded. This is the time period when a "peak" data rate is required. To satisfy this peak data rate, a certain pin count and data frequency on those pins must be available. A high peak data rate translates into a high pin count and/or high frequency, which increases device and/or system costs. A need exists for an SLM that reduces this peak data rate.